使用Quartus进行编译的过程中，出现以下报错，Verilog HDL Procedural Assignment error at tb.v(20): object "cap_flow" on left-hand side of assignment must have a variable data type



答：一般都是信号类型定义出错，原来定义为wire改为reg，或者reg的改为wire，请看：http://fpgabbs.com/forum.php?mod ... =621&fromuid=100110